1. Field of the Invention
The present invention relates in general to a power-on reset circuit. In particular, the present invention relates to a reset pulse generator.
2. Description of the Related Art
Power-on reset circuits are generally applied in semiconductor circuits to initialize the chip at startup.
FIG. 1 shows a conventional power-on reset circuit. A high logic-level reset signal RESET is generated when a low logic-level power-on pulse POWER_ON is input to an inverter 10, (a Schmitt trigger for example). In addition, the reset signal RESET can also be generated by operating the manual switch 12. The logic-level of the input terminal of the Schmitt trigger 10 drops to low-logic level when the switch 12 is turned on. Thus, the reset signal RESET with high logic-level is generated. The Schmitt trigger 10 outputs the reset signal RESET with high logic-level to the CPU 14, the CPU 14 is then initialized according to the high logic-level reset signal RESET.
However, only a single reset signal RESET is provided to the CPU 14 by the conventional power-on reset circuit. Thus, if the initialization fails because of a timing error or other unexpected reasons, the initialization can't be performed again without another reset signal RESET, thus, the system crashes. Another reset signal RESET can be generated by operating the manual switch 12, but this switch usually only exists when a product is designed or tested. There is usually no switch included on finished consumer products, thus, the system crashes because the CPU has not been initialized.